LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY Flipflop_top IS

PORT
(
set : IN STD_LOGIC;
reset : IN STD_LOGIC;
Q : OUT STD_LOGIC;
Q_strich : OUT STD_LOGIC
);


END Flipflop_top;

ARCHITECTURE Flipflop_top_architecture OF Flipflop_top IS

SIGNAL intern : std_LOGIC;

BEGIN

PROCESS (set,reset)

BEGIN

IF SET = '0' THEN

	intern <= '1';
END IF;

IF reset = '0' THEN

	intern <= '0';
END IF;

Q <= intern;
Q_Strich <= not intern;

END PROCESS;


END Flipflop_top_architecture;