LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY Seg_top IS

PORT
(
seg_in : IN STD_LOGIC_VECTOR (3 downto 0);
seg_out : OUT STD_LOGIC_VECTOR (6 downto 0)
);
END Seg_top;

ARCHITECTURE Seg_top_architecture OF Seg_top IS

signal bcd : std_logic_vector(3 downto 0);
signal seg7 : std_logic_vector (6 downto 0);

BEGIN

process (seg_in)

BEGIN

bcd <= not seg_in; -- Taster gedrückt = '0' !

	case bcd is

	when "0000" => seg7 <="0111111";
	when "0001" => seg7 <="0000110";
	when "0010" => seg7 <="1011011";
	when "0011" => seg7 <="1001111";
	when "0100" => seg7 <="1100110";
	when "0101" => seg7 <="1101101";
	when "0110" => seg7 <="1111100";
	when "0111" => seg7 <="0000111";
	when "1000" => seg7 <="1111111";
	when "1001" => seg7 <="1100111";
	when others => seg7 <="0000000";
	
	end case;
	
	seg_out <= not seg7; --Gemeinsame Anode '0' = Licht an!
	
end process;

END Seg_top_architecture;