LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY T_flipflop_top IS

PORT
(
	clk 		: IN STD_LOGIC;
	reset	 	: IN STD_LOGIC;
	Q 			: OUT STD_LOGIC
);

END T_flipflop_top;

ARCHITECTURE T_flipflop_top_architecture OF T_flipflop_top IS

signal intern :std_logic;

BEGIN

process(clk, reset)

begin

if rising_edge(clk) then

   if intern = '0' then 
	intern <= '1';
	else
	intern <= '0';	
	end if;
	
	if reset = '0' then
	intern <= '0';	
	end if;
	
end if;

Q <= intern;

end process;

END T_flipflop_top_architecture;