LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY zaehler_top IS

PORT
(
	clk 		: IN STD_LOGIC;
	reset	 	: IN STD_LOGIC;
	A_out, B_out, C_out, D_out : out std_logic
);

END zaehler_top;

ARCHITECTURE Zaehler OF zaehler_top IS

component flipflop

PORT
(
	clk 		: IN STD_LOGIC;
	reset	 	: IN STD_LOGIC;
	Q 			: OUT STD_LOGIC;
	Q_strich	: OUT STD_LOGIC
);

end component;

signal takt_Q			: std_logic_vector(3 downto 0);
signal takt_Q_strich	: std_logic_vector(3 downto 0);

begin

flip0:for i in 0 to 4 generate

 flip1: 	if (i = 0) generate
			Bit3: flipflop
			port map (clk,reset,takt_Q(0),takt_Q_strich(0));	
			end generate;

 flip2: 	if (i >0) and (i < 4) generate
			Biti: flipflop
			port map (takt_Q(i-1),reset,takt_Q(i),takt_Q_strich(i)); 
			end generate; 
 
end generate;
 
 A_out <= takt_Q(0);
 B_out <= takt_Q(1);
 C_out <= takt_Q(2);
 D_out <= takt_Q(3);
 

END Zaehler;